The present invention relates to a PLL (phase locked loop) circuit, and more specifically to a PLL circuit used for a clock generation and a data reproduction.
In the field of communication, a PLL circuit is widely used for extracting a clock component from a received data. In the PLL circuit used for a clock or data regeneration, when the clock component is extracted from the received data, a phase comparing circuit is used for comparing the phase where the data changes, with the phase of a clock generated in the PLL circuit, so as to detect a phase difference. This phase comparing circuit can be classified into two types based on the method for outputting a difference in phase between two input signals. Namely, a first type is a so called linear system for outputting the phase difference in an analog expression, and a second type is a binary system of expressing the phase difference by only a binary value.
In the linear system, the width of a phase difference signal is caused to change in accordance with the phase difference, so that the output of the phase comparing circuit includes the information indicative of the degree of the phase difference. In the binary system, on the other hand, only which of the two input signal is in advance is discriminated for outputting the result of the comparison, and therefore, the information indicative of the degree of the phase difference does not exits. Accordingly, in the case of making a precise comparison, the linear system is used in many case. However, the phase comparing circuit of the binary system outputs the phase difference having the degree of precision inferior to that of the phase difference obtained in the linear system, but advantageously operates in a high speed.
Recently, with an elevation in the communication speed, the data speed and the clock speed handled in the PLL circuit for extracting the clock and the data are correspondingly elevated. Accordingly, it is required to increase the operation speed of the phase comparing circuit. The reason for this is that, since the phase comparing circuit used in the PLL circuit for the regeneration of the clock and the data compares the inputted transmission data and the clock generated in the PLL circuit, the phase comparing circuit is required to operate at the speed of the inputted data. Therefore, in the clock and data regenerating PLL circuit used in the high speed communication, the phase comparing circuit of the binary system capable of operating at a high speed is required in many cases.
Furthermore, in a multiplying PLL circuit configured to generate a clock which is in synchronism with an external clock and which has a clock frequency higher than that of the external clock, the clock frequency handled correspondingly becomes high. Therefore, the phase comparing circuit used in the multiplying PLL circuit is required to be correspondingly speeded up.
Referring to FIG. 10, there is shown a block diagram of one example of the clock and data regenerating PLL circuit using the prior art phase comparing circuit of the binary system. The shown PLL circuit comprises a phase comparing circuit 11, an up-down counter 13, a charge pump 14, a loop filter 15 and a VCO (voltage controlled oscillator) 16, which are connected as shown.
In this arrangement, an input signal and an output signal of the VCO 16 are supplied to the phase comparing circuit 11, where both the signals are phase-compared. The result of this phase comparison is outputted as a up signal 11u or a down signal 11d, which causes the up-down counter 13 to perform an up-count operation or a down-count operation.
The up-down counter 13 outputs a phase advancing signal S or a phase delaying signal T, which are supplied to the charge pump 14. This charge pump 14 includes a pair of transistors (not shown) which are operated by the phase advancing signal S or the phase delaying signal T, respectively, and which are connected in series between a power supply voltage and ground, so that an output is derived from a connection node between the pair of transistors.
An output of the charge pump 14 is supplied to the loop filter 15, so that a capacitor in the loop filter 15 is charged or discharged. The electric charge accumulated in this capacitor is supplied as a control voltage to the VCO 16, so that the oscillation frequency of the VCO is controlled. Namely, if the capacitor in the loop filter 15 is charged by the phase advancing signal S, the control voltage is elevated so that the oscillation frequency of the VCO is elevated. On the other hand, if the capacitor in the loop filter 15 is discharged by the phase delaying signal T, the control voltage is elevated so that the oscillation frequency of the VCO is lowered.
In brief, in the shown circuit, the oscillation frequency of the VCO 16 is controlled in accordance with the phase advanced or delayed condition, so that it is possible to obtain an oscillation output signal which has the same frequency as that of the input signal and which is in the same phase as that of the input signal.
Incidentally, the PLL circuit can be constituted by replacing the phase comparing circuit, with a frequency comparing circuit of a circuit which performs a frequency comparison and a phase comparison.
However, the output of the phase comparing circuit of the binary system is the up signal 11u or the down signal 11d having the constant width, which merely indicates either the phase advancement or the phase delay, for example as a phase difference signal having the width corresponding to one item of data. Therefore, in the phase comparing circuit of the binary system, even after the PLL circuit has become a stable condition, the phase comparing circuit continues to output the up signal 11u or the down signal 11d. Therefore, after the clock signal of the PLL circuit becomes the stable condition, the clock signal of the PLL circuit alternatively becomes in advance or delayed (this will be called a xe2x80x9cbang-bang operationxe2x80x9d hereinafter).
In the prior art, in order to make small the amount of change of the clock frequency caused by the bang-bang operation in the PLL circuit of the binary system, the output of the phase comparing circuit 11 is not supplied directly to the charge pump 14, but the up signal 11u and the down signal 11d are supplied to the up-down counter 13 to suppress the bang-bang operation. The up-down counter 13 is constituted of an adding/subtracting circuit which receives both the up signal 11u and the down signal 11d, so that when the total of the up signal 11u or the down signal 11d exceeds a certain value, the phase delaying signal T or the phase advancing signal S is outputted to the charge pump 14.
For example, it is assumed that the up signal and the down signal supplied to the up-down counter 13 is +1 and xe2x88x921, respectively and an initial value of the up-down counter 13 is xe2x80x9c0xe2x80x9d. For example, when the count value of the up-down counter 13 becomes +8, the phase advancing signal S is outputted to the charge pump 14, or when the count value of the up-down counter 13 becomes xe2x88x928, the phase delaying signal T is outputted to the charge pump 14. The bang-bang operation occurring when the PLL circuit becomes the stable condition is absorbed by the up-down counter 13, with the result that the PLL circuit has an increased degree of stability.
However, if the speed of the transmission signal becomes further high, the up-down counter formed of the adding/subtracting circuit becomes inoperable, with the result that the operation speed of the PLL circuit is limited by the up-down counter.
The reason for this is as follows: The up-down counter includes a synchronous circuit operating with the clock having the same frequency as that of the up signal or the down signal supplied to the up-down counter. In addition, when the phase comparing circuit of the binary system is used, the up signal and the down signal is outputted at a speed in accordance with the data transmission rate. For example, the data transmission rate is 1 Gb/s (b/s is bit per second), the up signal or the down signal is outputted at 1 Gb/s. Accordingly, the count operation of the up-down counter is executed at the period of 1 GHz.
The up-down counter is constituted of the adding/subtracting circuit. When this adding/subtracting circuit is constituted of a synchronous circuit operating in synchronism with the clock, the adding/subtracting circuit is constituted of a flipflop circuit and a selector. Accordingly, since the up signal and the down signal is inputted at a rate exceeding the operating speed of the adding/subtracting circuit, the up-down counter becomes inoperable. The rate of the up signal and the down signal changes in proportion to the data transmission rate.
For the reason mentioned above, if the data transmission rate becomes high, the up-down counter becomes inoperable. Accordingly, the speed-up of the operation is prevented by limiting the operation speed of the PLL circuit by the up-down counter.
Accordingly, it is an object of the present invention to provide a PLL circuit which has overcome the above mentioned defect of the prior art.
Another object of the present invention is to provide a PLL circuit having an elevated operation speed.
The above and other objects of the present invention are achieved in accordance with the present invention by a phase locked loop circuit comprising a phase comparing means for phase-comparing an input signal with an oscillation signal, an up-down counter having a count value is counted up or down in accordance with the result of phase comparison of the phase comparing means, an oscillating means for generating the oscillation signal having the frequency controlled in accordance with the count value of the up-down counter, wherein the result of phase comparison of the phase comparing means is a serial signal, and there is provided a serial-to-parallel converting means for converting the serial signal into a parallel signal, and the count value of the up-down counter is counted up or down in accordance with the parallel signal.
Here, for example, the serial signal is a signal having a constant width indicative of the result of phase comparison.
In addition, the serial-to-parallel converting means is constituted of a {1:n } demultiplexor circuit for converting the serial signal into the parallel signal composed of xe2x80x9cnxe2x80x9d bits where xe2x80x9cnxe2x80x9d is a natural number not less than xe2x80x9c2xe2x80x9d, for example, a {1:2} demultiplexor circuit for converting the serial signal into the parallel signal composed of xe2x80x9c2xe2x80x9d bits, or a {1:4} demultiplexor circuit for converting the serial signal into the parallel signal composed of xe2x80x9c4xe2x80x9d bits.
Furthermore, the input signal is a NRZ signal and the phase locked loop circuit regenerates a synchronous signal based on the NRZ signal. Alternatively, the input signal is an external signal and the phase locked loop circuit operates as a multiplying PLL circuit which regenerates a synchronous signal in synchronism with the external signal. Incidentally, the serial-to-parallel converting means is provided between the phase comparing means and the up-down counter.
As seen from the above, the phase locked loop circuit in accordance with the present invention is characterized by comprising a circuit for serial-to-parallel converting the result of comparison outputted from the phase comparing circuit that phase-compares the two signals. This serial-to-parallel converting means is constituted of a {1:n} demultiplexor circuit for converting the serial signal into the parallel signal composed of xe2x80x9cnxe2x80x9d bits where xe2x80x9cnxe2x80x9d is a natural number not less than xe2x80x9c2xe2x80x9d. In addition, the serial-to-parallel converting means is provided between the phase comparing means and the up-down counter.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.